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Implementation of a pulse coupled neural network in FPGA
J Waldemark1, M Millberg, T Lindblad
1Optronic Consult i Norden AB, Skellefteå, Sweden.
International Journal of Neural Systems
|September 30, 2000
Summary
This study presents a VHDL implementation of the Pulse Coupled Neural Network (PCNN) for FPGAs, achieving high throughput for image processing. The design enables efficient, re-configurable recognition systems on a single chip.
Area of Science:
- Computer Engineering
- Artificial Intelligence
- Image Processing
Background:
- Pulse Coupled Neural Networks (PCNN) are biologically inspired neural networks.
- PCNNs are applicable in various image analysis tasks, including segmentation and filtering.
- Real-time image pre-processing demands efficient computational architectures.
Purpose of the Study:
- To develop a VHDL implementation of a PCNN suitable for Field-Programmable Gate Arrays (FPGA).
- To achieve high-speed processing for time-critical image analysis applications.
- To explore the feasibility of a re-configurable recognition system on a single chip.
Main Methods:
- Designed a PCNN architecture using VHDL for FPGA implementation.
- Employed pipelining techniques to enhance processing throughput.
- Investigated re-configurable coefficients for system flexibility.
- Analyzed the impact of constant ranges and resolutions on hardware resource utilization.
Main Results:
- Achieved a high throughput of 55 million neuron iterations per second through pipelining.
- Demonstrated the potential for implementing a complete recognition system on one or two chips.
- Identified that optimizing constant ranges and resolutions can significantly reduce hardware requirements.
Conclusions:
- The VHDL implementation of PCNN on FPGA offers high performance for image processing.
- Re-configurable coefficients enhance the system's versatility for recognition tasks.
- Hardware resource optimization is crucial for efficient FPGA-based PCNN design.