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Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

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Limits on silicon nanoelectronics for terascale integration.

J D Meindl¹, Q Chen, J A Davis

¹School of Electrical and Computer Engineering, Microelectronics Research Center, Georgia Institute of Technology, Atlanta, GA 30332-0269, USA. james.meindl@mirc.gatech.edu

Science (New York, N.Y.)

|September 15, 2001

Summary

Silicon semiconductor technology offers vast potential for terascale integration (TSI), enabling over a trillion transistors per chip. Achieving this requires advanced double-gate transistors and overcoming interconnect challenges for future nanoelectronics.

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Area of Science:

Semiconductor technology
Nanoelectronics
Materials science

Background:

Silicon semiconductor technology has seen decades of exponential advancement in performance and productivity.
Concerns exist regarding the approaching physical limits of current silicon technology.

Purpose of the Study:

To analyze the fundamental, material, device, circuit, and system limits of silicon technology.
To determine the feasibility of achieving terascale integration (TSI).

Main Methods:

Analysis of fundamental scaling limits in semiconductor devices.
Modeling of double-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) at the nanoscale.
Evaluation of interconnect technologies for high-density integration.

Main Results:

Silicon technology retains significant potential for terascale integration (TSI), exceeding one trillion transistors per chip.
Feasibility is contingent on developing double-gate MOSFETs with specific nanoscale dimensions (1nm gate oxide, 3nm silicon channel, 10nm channel length).

Conclusions:

Terascale integration in silicon is achievable by overcoming current technological hurdles.
The primary challenge for realizing nanoelectronics for TSI lies in developing advanced interconnecting wires.