Logic gates and computation from assembled nanowire building blocks.

Area of Science:

• Nanotechnology and Materials Science
• Semiconductor Device Physics
• Integrated Circuit Design

Background:

• Traditional top-down electronics fabrication faces fundamental limitations for further miniaturization.
• Continued scaling of computing power is challenged by physical limits of current manufacturing methods.

Purpose of the Study:

• To introduce and validate a bottom-up fabrication strategy for electronic devices.
• To demonstrate the assembly of functional nanoscale electronic components using semiconductor nanowires.
• To explore the potential of nanowire-based structures for logic operations and computation.

Main Methods:

• Assembly of functional device elements and arrays from solution using semiconductor nanowires.
• Fabrication of crossed nanowire p-n junctions and junction arrays.
• Integration of nanowires as channel and gate electrodes in nanoscale field-effect transistor arrays.

Main Results:

• Achieved over 95% yield in assembling crossed nanowire p-n junctions with controllable electrical properties.
• Successfully created integrated nanoscale field-effect transistor arrays using nanowire building blocks.
• Configured nanowire junction arrays into OR, AND, and NOR logic gates demonstrating substantial gain.

Conclusions:

• The bottom-up approach using semiconductor nanowires offers a viable alternative to top-down fabrication.
• Nanowire junction arrays can be reliably fabricated and configured for complex logic functions.
• This method enables the implementation of basic computation at the nanoscale.