DPLL implementation in carrier acquisition and tracking for burst DS-CDMA receivers

Area of Science:

• Digital Signal Processing
• Telecommunications Engineering
• Spread Spectrum Communications

Background:

• Carrier offset presents a significant challenge in Code Division Multiple Access (CDMA) systems, impacting receiver performance.
• Existing digital phase locked loop (DPLL) architectures may have limitations in correcting maximum carrier offsets for diverse CDMA applications.
• Effective carrier synchronization is crucial for reliable data recovery in burst-mode packet communications.

Purpose of the Study:

• To present novel digital phase locked loop (DPLL) architectures for burst-mode packet Direct Sequence-CDMA (DS-CDMA) receivers.
• To address the challenge of carrier offset correction by proposing enhanced DPLL forms.
• To evaluate the performance and implementation considerations of these DPLL designs.

Main Methods:

• Discussion of a classical DPLL architecture.
• Introduction and analysis of two novel DPLL forms designed to widen the carrier offset acquisition range.
• Consideration of FPGA implementation for direct hardware deployment.

Main Results:

• The proposed novel DPLL forms significantly widen the carrier offset acquisition range compared to classical methods.
• The enhanced acquisition range is achieved without performance degradation, such as increased acquisition time or phase error variance.
• A maximum acquisition range of 1/(4T) (where T is the symbol period) is demonstrated by the novel DPLLs.

Conclusions:

• Novel DPLL architectures offer a superior solution for carrier offset correction in DS-CDMA burst-mode receivers.
• These designs provide an expanded acquisition range, crucial for robust communication systems.
• The DPLL solutions are suitable for direct implementation using Field-Programmable Gate Arrays (FPGAs).