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Information processing in long delay memory-guided saccades: further insights from TMS
Thomas Nyffeler1, Charles Pierrot-Deseilligny, Tobias Pflugshaupt
1Perception and Eye Movement Laboratory, Department of Neurology, University Hospital, University of Bern, Freiburgstrasse 10, 3010 Bern, Switzerland.
Experimental Brain Research
|October 28, 2003
Summary
Transcranial magnetic stimulation (TMS) over the dorsolateral prefrontal cortex (DLPFC) impaired memory-guided saccades. This interference was greater with shorter memory delays, suggesting DLPFC
Area of Science:
- Neuroscience
- Cognitive Psychology
- Experimental Psychology
Background:
- Spatial working memory is crucial for guiding behavior.
- The dorsolateral prefrontal cortex (DLPFC) is implicated in executive functions, including working memory.
- Understanding the temporal dynamics of DLPFC involvement in spatial memory is essential.
Purpose of the Study:
- To investigate the role of the dorsolateral prefrontal cortex (DLPFC) in spatial working memory using transcranial magnetic stimulation (TMS).
- To examine how memory delay duration influences the impact of DLPFC disruption on memory-guided saccades.
Main Methods:
- Eight healthy subjects performed memory-guided saccades with short (3s) and long (30s) memorization delays.
- Single-pulse TMS was applied over bilateral DLPFC 1s after target presentation.
- Error in saccade amplitude was measured as the primary outcome.
Main Results:
- TMS over the DLPFC significantly increased saccade errors in both delay conditions.
- The disruptive effect of TMS was significantly more pronounced during the short delay compared to the long delay.
- This suggests a time-dependent role for the DLPFC in spatial working memory.
Conclusions:
- The DLPFC plays a critical role in the early, serial processing stages of spatial working memory.
- During longer delays, spatial memory processing appears to involve parallel mechanisms less dependent on the DLPFC.
- A mixed model of spatial working memory, incorporating serial and parallel processing, is proposed.