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FAIR: a hardware architecture for real-time 3-D image registration
Carlos R Castro-Pareja1, Jogikal M Jagadeesh, Raj Shekhar
1Department of Electrical Engineering, The Ohio State University, Columbus, OH 43210, USA.
Summary
This study introduces a novel hardware architecture for accelerating mutual information-based image registration. The new design enables real-time 3-D medical image registration, significantly improving clinical efficiency.
Area of Science:
- Medical Imaging
- Computer Architecture
- Image Processing
Background:
- Mutual information-based image registration is crucial for medical imaging but computationally intensive.
- Current methods require minutes on single-processor computers, limiting clinical application.
- Accelerating this process is key to enabling routine clinical use.
Purpose of the Study:
- To present a hardware architecture for real-time three-dimensional (3-D) image registration.
- To overcome the computational bottlenecks of mutual information-based image registration.
- To facilitate the clinical adoption of advanced image registration techniques.
Main Methods:
- Developed a network of processing units with independent memory buses for image and histogram data.
- Implemented memory access parallelization and pipelining within each processing unit.
- Utilized partial volume interpolation for mutual information calculation.
Main Results:
- Achieved a 25-fold speedup per processing unit compared to processors with identical bus speeds.
- Demonstrated the feasibility of real-time 3-D image registration.
- The proposed architecture offers superior per-processor performance at a lower cost than supercomputers.
Conclusions:
- The novel hardware architecture significantly accelerates mutual information-based image registration.
- Real-time 3-D image registration is achievable, paving the way for enhanced clinical workflows.
- This cost-effective solution promises to promote the routine use of image registration in clinical settings.