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ACE16k: a 128x128 focal plane analog processor with digital I/O
Gustavo Liñan Cembrano1, Angel Rodríguez-Vázquez, Servando Espejo Meana
1Instituto de Microelectrónica de Sevilla - CNM-CSIC- Universidad de Sevilla, Edificio CICA Avda. Reina Mercedes s/n 41012, Seville, Spain.
International Journal of Neural Systems
|March 20, 2004
Summary
A new 128x128 Focal-Plane Analog Programmable Array Processor (FPAPAP) achieves 0.33 TeraOPS for real-time vision tasks. This analog processor offers high speed and moderate accuracy with efficient power consumption.
Area of Science:
- Computer Engineering
- Artificial Intelligence
- VLSI Design
Background:
- Real-time early-vision applications demand high-speed, moderate-accuracy processing.
- Traditional processors face limitations in meeting these demanding requirements.
Purpose of the Study:
- To introduce a novel 128x128 Focal-Plane Analog Programmable Array Processor (FPAPAP).
- To evaluate its system-level performance for early-vision tasks.
Main Methods:
- Fabrication using 0.35 microm standard digital 1P-5M CMOS technology.
- Design focused on analog computation for 90% of transistors.
- Digital interfaces for external data and control.
Main Results:
- Achieved peak computing performance of 0.33 TeraOPS.
- Maintained power efficiency at 82.5 GOPS/W.
- Demonstrated feasibility through preliminary experimental results.
Conclusions:
- The FPAPAP meets the high-speed and moderate-accuracy needs of real-time vision.
- The analog-centric design offers significant computational power and energy efficiency.