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Related Experiment Videos

Efficient implementation of accurate geometric transformations for 2-D and 3-D image processing.

Saul R Dooley1, Robert W Stewart, Tariq S Durrani

  • 1Philips Research Laboratories, Redhill, Surrey, RH5 1HA, UK. saul.dooley@philips.com

IEEE Transactions on Image Processing : a Publication of the IEEE Signal Processing Society
|August 26, 2004
PubMed
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This study introduces a hardware-efficient polynomial interpolator using Horner's scheme for high-quality image geometric transformations. This method enables efficient multidimensional interpolation for 2D and 3D images.

Area of Science:

  • Computer Vision
  • Image Processing
  • Digital Signal Processing

Background:

  • Geometric transformations are crucial for image manipulation.
  • Efficient hardware implementation of image processing algorithms is a significant challenge.
  • Polynomial interpolators offer high-quality results but can be computationally intensive.

Purpose of the Study:

  • To propose a novel polynomial interpolator structure based on Horner's scheme.
  • To demonstrate the hardware efficiency and high-quality performance of the proposed structure.
  • To facilitate efficient multidimensional interpolation for 2D and 3D images.

Main Methods:

  • Utilizing a polynomial interpolator structure based on Horner's scheme.
  • Implementing polynomial-based interpolators, including cubic B-splines and optimal interpolators of shortest support.

Related Experiment Videos

  • Exploring hardware/software partitioning for efficient implementation.

    • Main Results:

    • The proposed Horner-based structure is efficiently realizable in hardware.
    • Exact implementation of cubic B-splines and optimal interpolators is achieved within the Horner framework.
    • The structure enables efficient multidimensional interpolation.

    Conclusions:

    • The Horner-based polynomial interpolator structure offers an efficient hardware solution for high-quality geometric image transformations.
    • This approach is suitable for both two- and three-dimensional image processing.
    • The proposed structure supports effective hardware/software partitioning for optimized performance.