Lamination method for the study of interfaces in polymeric thin film transistors

Michael L Chabinyc1, Alberto Salleo, Yiliang Wu

  • 1Palo Alto Research Center, 3333 Coyote Hill Road, Palo Alto, California 94304, USA. mchabinyc@parc.com

Summary

A novel lamination method enables fabrication of polymer thin-film transistors (TFTs). This technique enhances polymer semiconductor performance, suggesting molecular ordering, not interface electronics, dictates TFT mobility.

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