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Related Experiment Videos

NEUROM: a ROM based RNS digital neuron.

Giuseppe Alia1, Enrico Martinelli

  • 1Dipartimento di Ingegneria dell'Informazione, Università di Pisa, Via Caruso, 56100 Pisa, Italy. g.alia@iet.unipi.it

Neural Networks : the Official Journal of the International Neural Network Society
|March 30, 2005
PubMed
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This study introduces NEUROM, a fast digital device for artificial neurons using residue number systems (RNS) and look-up tables for high-speed computation. The design achieves rapid response times, enabling efficient integration into VLSI chips.

Area of Science:

  • Digital hardware design
  • Artificial intelligence hardware
  • Computer arithmetic

Background:

  • Artificial neurons are crucial for AI but require efficient hardware implementations.
  • Traditional floating-point arithmetic can be computationally intensive for neuron functions.
  • Residue Number Systems (RNS) offer potential for parallel and fast computations.

Purpose of the Study:

  • To design and evaluate a fast digital device for implementing artificial neurons.
  • To leverage residue arithmetic and look-up tables for enhanced computational speed.
  • To achieve accuracy comparable to 20-bit floating-point systems.

Main Methods:

  • Mapping floating-point data to integer residue representation.
  • Utilizing residue arithmetic operations for neuron functions.

Related Experiment Videos

  • Employing table look-up techniques for computation.
  • Designing a residue neuron (NEUROM) with 12 inputs.

    • Main Results:

    • NEUROM achieves a response time of approximately 80 ns (8 x ROM access time).
    • Pipeline mode operation reduces delay to about 14 ns.
    • The design offers high throughput suitable for VLSI integration.
    • Achieved accuracy is comparable to or better than 20-bit floating-point systems.

    Conclusions:

    • The proposed residue neuron design (NEUROM) offers maximum throughput compared to existing literature.
    • The RNS carry independence property and look-up tables significantly speed up computations.
    • Integration of multiple NEUROM units on a single chip is feasible with current VLSI technology.
    • Memory usage can be optimized at the cost of response time.