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Design and implementation of High Performance Visual Stimulator for Brain Computer Interfaces.

V Jaganathan1, T M Srihari Mukesh, M Ramasubba Reddy

  • 1Biomedical Engineering Division, Department of Applied Mechanics Indian Institute of Technology-Madras Chennai 600036, India.

Conference Proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference
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Summary

A new algorithm enables generic computers to create accurate visual stimuli for Brain Computer Interfaces (BCIs). This system precisely displays multiple patterns for Steady State Visual Evoked Potential (SSVEP) detection.

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Area of Science:

  • Biomedical Engineering
  • Neuroscience
  • Computer Science

Background:

  • Brain Computer Interfaces (BCIs) often require precise visual stimuli for operation.
  • Existing visual stimulation methods may lack accuracy or flexibility on generic hardware.

Purpose of the Study:

  • To develop an algorithm for implementing accurate visual stimulators on generic computers for BCIs.
  • To enable simultaneous display of multiple patterns for Steady State Visual Evoked Potential (SSVEP) stimulation.

Main Methods:

  • Developed an algorithm utilizing hardware counters on generic computers for precise timing.
  • Implemented simultaneous display of 20 distinct visual patterns modulated at various frequencies.
  • Designed for easy modification of stimulation patterns for SSVEP.

Main Results:

  • The algorithm achieves high accuracy, with less than 0.73% error.
  • Demonstrated high precision, showing a 0.1% coefficient of variation.
  • Successfully tested with 20 patterns at frequencies ranging from 6 Hz to 15 Hz.

Conclusions:

  • The developed algorithm provides an accurate and flexible solution for visual stimulation in BCI applications.
  • Leveraging hardware counters ensures reliable timing for SSVEP-based BCIs.
  • This approach enhances the feasibility of advanced BCI systems using readily available computing hardware.