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Real-time system for high-image resolution disparity estimation.

Javier Díaz, Eduardo Ros, Richard Carrillo

    IEEE Transactions on Image Processing : a Publication of the IEEE Signal Processing Society
    |February 8, 2007
    PubMed
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    This study introduces a fast, hardware-based depth estimation technique using phase measurement, offering superior noise resistance and speed for real-time applications.

    Area of Science:

    • Computer Vision
    • Hardware Engineering
    • Signal Processing

    Background:

    • Standard stereo vision systems face challenges with phase warping, camera noise, and distortion.
    • Real-time depth estimation requires efficient and robust computational architectures.

    Purpose of the Study:

    • To present a novel hardware implementation for fast depth estimation using phase measurement.
    • To overcome limitations of traditional stereo vision methods in terms of noise susceptibility and phase warping.

    Main Methods:

    • Developed a hardware architecture leveraging Field-Programmable Gate Array (FPGA) devices for parallel processing.
    • Designed a fine-grain pipeline structure integrated with a custom frame-grabber module.
    • Implemented depth estimation based on phase measurement, analyzing degradation from bit quantization errors.

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    Main Results:

    • Achieved a computation speed of 65 megapixels per second.
    • Processed 52 frames per second at a resolution of 1280 x 960 pixels.
    • Demonstrated reduced susceptibility to camera noise and distortion compared to block-matching stereo systems.

    Conclusions:

    • The proposed phase measurement technique provides a simple, fast, and robust solution for hardware-based depth estimation.
    • FPGA implementation enables high-speed processing suitable for real-time applications.
    • The system's performance is competitive and adaptable through user-selectable Gabor-scale circuits.