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Efficient architectures for two-dimensional discrete wavelet transform using lifting scheme.

Chengyi Xiong1, Jinwen Tian, Jian Liu

  • 1College of Electronic Information Engineering, South-Center University for Nationalities, Wuhan 430074, China. xiongcy@scuec.edu.cn

IEEE Transactions on Image Processing : a Publication of the IEEE Signal Processing Society
|March 16, 2007
PubMed
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This paper introduces novel architectures for discrete wavelet transform (DWT) using lifting schemes. New 1-D and 2-D DWT designs offer efficient hardware utilization and improved throughput rates for image processing.

Area of Science:

  • Digital Signal Processing
  • Image Processing
  • Hardware Architectures

Background:

  • Discrete Wavelet Transform (DWT) is crucial for signal and image processing.
  • Existing DWT architectures face challenges in hardware efficiency and speed.
  • Lifting schemes offer a flexible approach to DWT implementation.

Purpose of the Study:

  • To propose novel, efficient architectures for 1-D and 2-D Discrete Wavelet Transform (DWT) using lifting schemes.
  • To optimize DWT architectures for reduced hardware cost and increased throughput.
  • To present a trade-off analysis of hardware cost, throughput, latency, and complexity.

Main Methods:

  • Developed a 1-D DWT architecture using an embedded decimation technique.
  • Proposed a line-based 2-D DWT architecture (Fast Architecture - FA) leveraging parallel and pipeline techniques.

Related Experiment Videos

  • Introduced a high-speed architecture exploiting parallelism in lifting-based 2-D DWT.

    • Main Results:

    • The proposed 1-D DWT architecture alternates low- and high-frequency components.
    • The Fast Architecture (FA) achieves J levels of decomposition for N*N images in ~2N^2(1-4^-J)/3 clock cycles.
    • The high-speed architecture achieves J levels of decomposition in ~N^2(1-4^-J)/3 clock cycles, doubling throughput with minimal hardware increase.

    Conclusions:

    • The proposed 1-D and 2-D DWT architectures provide efficient solutions for digital signal processing.
    • These architectures offer a favorable trade-off between hardware cost, throughput rate, and control complexity.
    • The high-speed architecture presents a significant improvement in processing efficiency for image decomposition.