Extremely scaled 3-dimensional multiple-gate technologies for terabit era.

Area of Science:

• Semiconductor device physics
• Nanotechnology
• Materials science

Background:

• Scaling silicon devices to sub-5 nm is crucial for next-generation electronics.
• Traditional device architectures face significant challenges at these dimensions.
• Advanced gate structures are needed to overcome short-channel effects and improve performance.

Purpose of the Study:

• To propose and fabricate an all-around gate FinFET with a floating body for sub-5 nm feature sizes.
• To investigate and optimize solutions for critical issues in sub-10 nm device scaling.
• To demonstrate the feasibility of ultra-scaled FinFETs for room-temperature operation.

Main Methods:

• Design and fabrication of an all-around gate FinFET with an extremely narrow silicon fin.
• Intensive study and optimization of short channel effects, punchthrough, and series resistance.
• Characterization of device performance with a 3 nm fin width and 1.2 nm equivalent oxide thickness (EOT).

Main Results:

• Successful fabrication of a sub-5 nm all-around gate FinFET.
• Demonstration of optimized device characteristics addressing key scaling challenges.
• Achieved a 3 nm fin width and 1.2 nm EOT, a first for this device type.

Conclusions:

• The proposed all-around gate FinFET is a viable architecture for sub-5 nm silicon-based devices.
• This technology enables room-temperature operation of ultra-scaled transistors.
• Further development holds promise for advancing semiconductor technology.