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An Experimental Protocol for Assessing the Performance of New Ultrasound Probes Based on CMUT Technology in Application to Brain Imaging
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Simulation and experimental characterization of a 2-D capacitive micromachined ultrasonic transducer array element

O Oralkan1, X Jin, F L Degertekin

  • 1Edward L. Ginzton Lab., Stanford Univ., CA.

IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control
|February 5, 2008
PubMed

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Parallel plate capacitors consist of two conducting plates separated by a certain distance. However, it is mechanically difficult to hold the large plates parallel to each other without actual contact. Hence, a dielectric layer is commonly placed between the plates, which provides an easy solution for holding the plates together with a small gap and increases the capacitance of the capacitor.
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In integrated circuit technology, a capacitance multiplier is often utilized to produce a larger capacitance value when a small physical capacitance falls short. This is achieved by a circuit that multiplies capacitance values by a factor of up to 1000, such that a 10-pF capacitor can replicate the performance of a 100-nF capacitor.
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