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Related Experiment Video

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Recording and Analyzing Multimodal Large-Scale Neuronal Ensemble Dynamics on CMOS-Integrated High-Density Microelectrode Array
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IP core implementation of a self-organizing neural network.

D C Hendry1, A A Duncan, N Lightowler

  • 1Dept. of Eng., Univ. of Aberdeen, UK.

IEEE Transactions on Neural Networks
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This research details a flexible soft intellectual property (IP) core for self-organizing neural networks. The design offers high performance, achieving over 2 million classifications per second in a standard digital process.

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Area of Science:

  • Computer Engineering
  • Artificial Intelligence
  • Neural Networks

Background:

  • Previous work involved a 0.65-/spl mu/m single silicon chip with 256 neurons.
  • Migrating to a soft IP core introduces challenges in area, power, and clock speed.

Purpose of the Study:

  • To report on the design and performance of a soft IP core for a self-organizing neural network.
  • To explore parameterization opportunities for meeting diverse end-user requirements.

Main Methods:

  • Implementation of a single instruction multiple data (SIMD) array of neurons.
  • Development of an array controller (AC) using a RISC processor for instruction and data stream management.
  • Synthesis time parameterization for neuron count, reference vector elements, and element bit precision.

Main Results:

  • Achieved over 2,000,000 classifications per second with 256 neurons and 16 elements per reference vector on a 0.18-/spl mu/m process.
  • Demonstrated efficient area, power, and classification speed performance.
  • The parameterized design allows a single soft core to serve multiple end-user needs.

Conclusions:

  • The soft IP core implementation of a self-organizing neural network is feasible and offers significant performance.
  • Parameterization at synthesis time enhances design flexibility and reusability for various applications.
  • The integration with a RISC-based array controller ensures efficient data and instruction flow.