Neuron-synapse IC chip-set for large-scale chaotic neural networks

Area of Science:

• Neuromorphic Engineering
• Analog Circuit Design
• Digital Circuit Design

Background:

• Chaotic neural networks (CNNs) offer unique computational capabilities but require significant hardware resources.
• Implementing large-scale CNNs with high fidelity and scalability presents a major engineering challenge.

Purpose of the Study:

• To propose and validate a novel neuron-synapse integrated circuit (IC) chip-set for constructing large-scale chaotic neural networks.
• To enable the faithful reproduction of complex chaotic dynamics using analog and digital circuit techniques.

Main Methods:

• Switched-capacitor (SC) circuit techniques were employed to implement a three-internal-state transiently-chaotic neural network model.
• A digital synapse chip with a memory-based architecture was designed for rapid weighted summation calculations.
• Both SC neuron and digital synapse circuits were fabricated as ICs and extensively tested.

Main Results:

• The SC chaotic neuron chip accurately reproduces complex chaotic dynamics using continuous analog state variables.
• Digital control of model parameters was achieved via programmable capacitive arrays.
• The fabricated chip-set demonstrated successful function and performance for large-scale CNNs.

Conclusions:

• The proposed neuron-synapse IC chip-set provides a scalable and reconfigurable platform for building large-scale chaotic neural networks.
• This hardware advancement facilitates the exploration of complex dynamics in systems with up to 10,000 neurons and 10,000^2 synaptic connections.