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Accelerated image processing on FPGAs.

Bruce A Draper1, J Ross Beveridge, A P Willem Böhm

  • 1Department of Computer Science, Colorado State University, Fort Collins, CO 80523, USA. draper@cs.colostate.edu

IEEE Transactions on Image Processing : a Publication of the IEEE Signal Processing Society
|February 5, 2008
PubMed
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The Cameron project

Area of Science:

  • Computer Engineering
  • Hardware Acceleration
  • Embedded Systems

Background:

  • Single Assignment C (SA-C) is a novel programming language.
  • Field-Programmable Gate Arrays (FPGAs) offer high performance for specific tasks.
  • Image-based applications require significant computational resources.

Purpose of the Study:

  • To evaluate the performance of SA-C for image-based applications on FPGAs.
  • To compare SA-C/FPGA performance against traditional processor-based implementations.
  • To demonstrate the effectiveness of the SA-C compiler for hardware mapping.

Main Methods:

  • Applications were implemented using Single Assignment C (SA-C).
  • SA-C code was compiled to an Annapolis Microsystems (AMS) WildStar board with a Xilinx XV2000E FPGA.

Related Experiment Videos

  • Performance was benchmarked against equivalent applications in assembly and C on an 800 MHz Pentium III processor.

    • Main Results:

    • SA-C applications compiled to FPGAs achieved performance gains of 8x to 800x.
    • FPGA implementations significantly outperformed traditional CPU execution for image-based tasks.
    • The SA-C compiler successfully mapped complex applications to hardware.

    Conclusions:

    • SA-C and FPGA co-design provides substantial performance improvements for image processing.
    • This approach offers a viable alternative to traditional software execution for computationally intensive applications.
    • The Cameron project's technology demonstrates significant potential for accelerating embedded systems.