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Closed-loop Neuro-robotic Experiments to Test Computational Properties of Neuronal Networks
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Published on: March 2, 2015

Elementary function generators for neural-network emulators.

S Vassiliadis1, M Zhang, J G Delgado-Frias

  • 1Department of Electrical Engineering, Delft University of Technology, 2638 CD Delft, The Netherlands.

IEEE Transactions on Neural Networks
|February 6, 2008
PubMed
Summary
This summary is machine-generated.

Novel schemes for elementary function generators in neural-network emulators are proposed. These designs optimize hardware usage and computational efficiency for improved performance in artificial intelligence applications.

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Area of Science:

  • Computer Engineering
  • Artificial Intelligence
  • Digital Systems Design

Background:

  • Neural-network emulators require efficient elementary function generators.
  • Existing methods may be hardware-intensive or computationally complex.

Purpose of the Study:

  • To design novel, hardware-efficient elementary function generators for neural-network emulators.
  • To explore both first- and second-order approximation schemes.
  • To evaluate performance in terms of hardware cost and computational delay.

Main Methods:

  • Piece-wise first- and second-order approximations were employed.
  • Three novel first-order schemes with varying hardware requirements were developed.
  • Bit-serial implementations were considered to minimize hardware costs.

Main Results:

  • First-order schemes offer trade-offs between lookup table size, multiplications, and additions.
  • A second-order approximation yields higher precision but requires more hardware and has a larger delay.
  • Delays range from 24 to 32 bit-serial machine cycles across schemes.

Conclusions:

  • The proposed schemes provide flexible options for designing elementary function generators.
  • Hardware cost and precision can be balanced based on application needs.
  • The approach is adaptable for computing other elementary functions.