Digitally programmable analog building blocks for the implementation of artificial neural networks

Area of Science:

• Analog computing
• Artificial neural networks
• VLSI design

Background:

• Developing efficient analog hardware for artificial neural networks (ANNs) is crucial for high-performance, low-power computation.
• Existing synapse architectures often face limitations in signal range, resolution, and on-chip programmability.

Purpose of the Study:

• To design, experimentally characterize, and model homogeneous building blocks for analog feed-forward ANNs.
• To introduce and validate a novel synapse architecture with improved performance characteristics.

Main Methods:

• Design of a novel synapse architecture utilizing a quasi-passive digital-to-analog converter and a four-quadrant analog-digital multiplier.
• Implementation of neurons using metal-oxide semiconductor (MOS) transistors in saturation, leveraging their quadratic characteristics.
• Fabrication of a prototype chip in 1.2 µm CMOS technology for experimental validation.
• Mixed-signal simulation using behavior models derived from experimental characterization data.

Main Results:

• The proposed synapse architecture offers increased signal input range, improved area/weight resolution ratio, on-chip refreshing, and serial weight loading.
• Experimental results from the prototype chip demonstrate good agreement with design specifications.
• Behavior models accurately represent the fabricated analog components.

Conclusions:

• The developed homogeneous building blocks and novel synapse architecture are suitable for constructing analog feed-forward ANNs.
• The experimental validation and behavioral modeling confirm the efficacy and potential of the proposed analog ANN components.