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Updated: Jul 7, 2026

A Rapid Method for Modeling a Variable Cycle Engine

A Rapid Method for Modeling a Variable Cycle Engine

Published on: August 13, 2019

A parallel processing VLSI BAM engine.

S R Hasan¹, N K Siong

¹VLSI Res. Lab., Universiti Sains Malaysia, Perak.

IEEE Transactions on Neural Networks

|January 1, 1997

Summary

This study introduces the sliding feeder BAM array processor (SLiFBAM), a novel architecture for adaptive bidirectional associative memory (BAM) neural networks. The SLiFBAM enables efficient parallel processing for VLSI implementation, enhancing neural network performance.

Area of Science:

Computer Engineering
Artificial Intelligence
Neuroscience

Background:

Adaptive bidirectional associative memory (BAM) neural networks are crucial for pattern recognition and associative tasks.
Existing VLSI implementations face challenges in efficiently harnessing the inherent parallelism of BAM networks.
The need for scalable and high-performance neural network hardware drives research into novel architectures.

Purpose of the Study:

To explore emerging parallel/distributed architectures for digital VLSI implementation of adaptive BAM neural networks.
To develop a novel, efficient, and scalable neural processor architecture for adaptive BAM.
To design and describe a VLSI processor chip based on the proposed architecture.

Main Methods:

Development of a Single Instruction Stream Many Data Stream (SIMD)-based parallel processing architecture tailored for adaptive BAM.

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A Rapid Method for Modeling a Variable Cycle Engine

A Rapid Method for Modeling a Variable Cycle Engine

Published on: August 13, 2019

Introduction of the sliding feeder BAM array processor (SLiFBAM) with four operating modes: learn pattern, evaluate pattern, read weight, and write weight.

Design and fabrication of a SLiFBAM VLSI processor chip using 2-μm scalable CMOS technology.

Main Results:

A novel SLiFBAM processor architecture was developed, leveraging BAM's inherent parallelism.
A SLiFBAM VLSI processor chip with 4+4 neurons and local SRAM was successfully integrated on a prototype die.
The architecture's modularity allows for the construction of larger BAM networks up to 252 neurons.

Conclusions:

The SLiFBAM architecture offers a highly flexible and modular solution for VLSI implementation of adaptive BAM neural networks.
The developed SLiFBAM processor chip demonstrates the feasibility of efficient parallel processing for neural network hardware.
This work paves the way for constructing larger, high-performance adaptive BAM systems through scalable modular integration.