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Hardware implementation of CMAC neural network with reduced storage requirement
1Dept. of Electron. Eng., Kao Yuan Jr. Coll. of Technol. and Commerce, Kaohsiung.
IEEE Transactions on Neural Networks
|January 1, 1997
Summary
This study introduces a direct weight address mapping method for Cerebellar Model Articulation Controller (CMAC) neural networks. This approach significantly improves memory utilization and speeds up computations, demonstrated with a color calibration prototype.
Area of Science:
- Artificial Intelligence
- Neural Networks
- Computer Engineering
Background:
- Cerebellar Model Articulation Controller (CMAC) neural networks offer fast convergence and low computational complexity.
- A key limitation of CMAC is its inefficient weight memory utilization.
Purpose of the Study:
- To address the low storage space utilization rate in CMAC weight memory.
- To enhance the efficiency and reduce the memory footprint of CMAC implementations.
Main Methods:
- A novel direct weight address mapping approach was developed.
- A pipeline architecture was designed to optimize addressing operations.
- A CMAC hardware prototype was implemented for validation.
Main Results:
- The direct weight address mapping approach achieves near 100% weight memory utilization.
- The proposed architecture accelerates the computation of weight addresses.
- The hardware prototype successfully demonstrated the effectiveness of the approach for color calibration.
Conclusions:
- The direct weight address mapping approach significantly improves CMAC memory efficiency.
- The developed pipeline architecture enhances computational speed for addressing operations.
- The CMAC hardware prototype validates the proposed method for practical applications like color calibration.
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