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The design of a neuro-microprocessor
J Wawrzynek1, K Asanovic, N Morgan
1California Univ., Berkeley, CA.
IEEE Transactions on Neural Networks
|January 1, 1993
Abstract:
The architecture of a neuro-microprocessor is presented. This processor was designed using the results of careful analysis of a set of applications and extensive simulation of moderate-precision arithmetic for back-propagation networks. Simulated performance results and test-chip results for the processor are presented. This work is an important intermediate step in the development of a connectionist network supercomputer.
