A generic systolic array building block for neural networks with on-chip learning

C Lehmann1, M Viredaz, F Blayo

  • 1Micro-Comput. Lab., Swiss Federal Inst. of Technol., Lausanne.

Summary

This study presents a novel digital VLSI architecture for neural networks, utilizing generic building blocks for on-chip learning. This flexible design enables efficient hardware for diverse neural network models, moving beyond specific applications.

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