Jove
Visualize
Contact Us
JoVE
x logofacebook logolinkedin logoyoutube logo
ABOUT JoVE
OverviewLeadershipBlogJoVE Help Center
AUTHORS
Publishing ProcessEditorial BoardScope & PoliciesPeer ReviewFAQSubmit
LIBRARIANS
TestimonialsSubscriptionsAccessResourcesLibrary Advisory BoardFAQ
RESEARCH
JoVE JournalMethods CollectionsJoVE Encyclopedia of ExperimentsArchive
EDUCATION
JoVE CoreJoVE BusinessJoVE Science EducationJoVE Lab ManualFaculty Resource CenterFaculty Site
Terms & Conditions of Use
Privacy Policy
Policies

Related Experiment Videos

An adaptive neural processing node.

J Donald1, L Akers

  • 1Center for Solid State Electron. Res., Arizona State Univ., Tempe, AZ.

IEEE Transactions on Neural Networks
|January 1, 1993
PubMed
Summary
This summary is machine-generated.

Related Concept Videos

You might also read

Related Articles

Articles linked to this work by shared authors, journal, and citation graph.

Sort by
Same author

The inner ear of the Port Jackson shark, Heterodontus portusjacksoni: morphometric analysis using bioimaging and phalloidin staining.

Hearing research·2025
Same author

Enhanced GPR data interpretation to estimate in situ water saturation in a landfill.

Waste management (New York, N.Y.)·2021
Same author

Enhanced GPR data interpretation to estimate in situ water saturation in a landfill.

Waste management (New York, N.Y.)·2020
Same author

Identification of a bipolar disorder susceptibility locus on chromosome 15Q.

Acta neuropsychiatrica·2016
Same author

Investigation of the index case herd and identification of the genotypes of Theileria orientalis associated with outbreaks of bovine anaemia in New Zealand in 2012.

New Zealand veterinary journal·2015
Same author

Bag of worms.

Australasian radiology·2007
Same journal

Universal perceptron and DNA-like learning algorithm for binary neural networks: LSBF and PBF implementations.

IEEE transactions on neural networks·2013
Same journal

Guest editorial: special section on white box nonlinear prediction models.

IEEE transactions on neural networks·2011
Same journal

Data-based fault-tolerant control of high-speed trains with traction/braking notch nonlinearities and actuator failures.

IEEE transactions on neural networks·2011
Same journal

Guest editorial: special section on data-based control, modeling, and optimization.

IEEE transactions on neural networks·2011
Same journal

Neural network-based multiple robot simultaneous localization and mapping.

IEEE transactions on neural networks·2011
Same journal

Data-driven model-free adaptive control for a class of MIMO nonlinear discrete-time systems.

IEEE transactions on neural networks·2011
See all related articles

Two analog adaptive VLSI chips were designed and tested. These chips efficiently extract dominant features from input data using pulse coded signals and analog weights for neural processing.

Area of Science:

  • Artificial Intelligence
  • Computer Engineering
  • Neuroscience

Background:

  • Analog adaptive very-large-scale integration (VLSI) chips offer potential for efficient neural information processing.
  • Existing weight modification rules require further hardware implementation for practical applications.

Purpose of the Study:

  • To design and test two analog adaptive VLSI processing chips.
  • To demonstrate the chips' ability to perform feature extraction and neural processing.

Main Methods:

  • The chips utilize pulse coded signals for inter-node communication and analog weights for information storage.
  • On-chip weight modification rules are implemented based on Oja's rule and extensions by Leen and Sanger.
  • The adaptation rule incorporates fixed inputs and a variable lateral inhibition mechanism.

Related Experiment Videos

Main Results:

  • The first chip successfully demonstrated the functionality of individual processing node components, including forward transfer, weight modification, and inhibition.
  • The second chip's array of processing elements effectively extracted dominant features from input data.
  • The network produced linearly separable outputs, enabling efficient subsequent neural processing.

Conclusions:

  • The developed analog adaptive VLSI chips are capable of efficient feature extraction and neural processing.
  • The experimental results validate the on-chip implementation of adaptive algorithms for real-world applications.
  • These chips provide a foundation for more complex neural network architectures and processing tasks.