Analog implementation of a Kohonen map with on-chip learning

Area of Science:

• Artificial Intelligence
• Computer Engineering
• Neuroscience

Background:

• Kohonen maps are self-organizing neural networks for data classification.
• Current implementations often rely on conventional computers or specialized hardware.
• The computational demands of Kohonen maps suggest suitability for dedicated hardware solutions.

Purpose of the Study:

• To propose a fully analog Very Large Scale Integration (VLSI) implementation of a one-dimensional Kohonen map.
• To leverage on-chip learning and analog synaptic weight storage for improved performance.
• To demonstrate the feasibility of VLSI Kohonen maps using analog techniques.

Main Methods:

• Development of a fully analog one-dimensional Kohonen map architecture.
• Implementation of on-chip learning and refreshment mechanisms for analog synaptic weights.
• Utilizing current copier principles for analog synaptic weight storage.

Main Results:

• The proposed analog VLSI design achieves high parallelism due to a reduced transistor count per cell.
• On-chip learning and analog weight storage significantly enhance computation speed.
• Successful realization of VLSI Kohonen maps using the described analog techniques.

Conclusions:

• Analog VLSI implementation offers a promising approach for efficient Kohonen map realization.
• The proposed method provides a significant speed improvement over conventional implementations.
• This work validates the use of current copier-based analog synaptic weight storage for VLSI Kohonen maps.