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Related Experiment Videos

A charge-based on-chip adaptation Kohonen neural network.

Y He1, U Cilingiroglu

  • 1Dept. of Electr. Eng., Texas AandM Univ., College Station, TX.

IEEE Transactions on Neural Networks
|January 1, 1993
PubMed
Summary
This summary is machine-generated.

A novel charge-based neural network circuit with on-chip synapse adaptation was developed. This low-power, high-density circuit demonstrates successful unsupervised learning and classification.

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Area of Science:

  • Artificial Intelligence
  • Neuromorphic Engineering
  • VLSI Design

Background:

  • Traditional neural network hardware faces challenges in power consumption and density.
  • On-chip learning and adaptation are crucial for efficient AI hardware.
  • Kohonen neural networks (KNNs) are effective for unsupervised learning and pattern recognition.

Purpose of the Study:

  • To propose and demonstrate a charge-based on-chip synapse adaptation Kohonen neural network circuit.
  • To achieve low power dissipation and high synapse density.
  • To validate the circuit's unsupervised learning and classification capabilities.

Main Methods:

  • Design and fabrication of a prototype chip using 2-mum standard CMOS technology.
  • Implementation of a charge transfer mechanism for synapse adaptation.
  • Integration of novel compact device configurations for high density.
  • Experimental validation of unsupervised learning and classification.

Main Results:

  • Successful fabrication of a 12x10 synapse prototype chip with a density of 190 synapses/mm(2).
  • Demonstration of low power dissipation due to the charge transfer mechanism.
  • Experimental validation of unsupervised learning and classification capabilities, matching theoretical predictions.

Conclusions:

  • The proposed charge-based on-chip synapse adaptation KNN circuit offers a promising solution for low-power, high-density neuromorphic hardware.
  • The prototype chip successfully demonstrated unsupervised learning and classification, validating the design principles.
  • This approach paves the way for more efficient and scalable artificial intelligence systems on chip.