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Classification of Systems-I01:26

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Closed-loop Neuro-robotic Experiments to Test Computational Properties of Neuronal Networks
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Learning in linear systolic neural network engines: analysis and implementation.

S R Jones1, K M Sammut, J Hunter

  • 1Dept. of Electron. and Electr. Eng., Loughborough Univ. of Technol.

IEEE Transactions on Neural Networks
|January 1, 1994
PubMed
Summary

This study analyzes training algorithms on linear systolic arrays for neural networks. It identifies optimal hardware structures and controller designs for cost-effective implementation.

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Area of Science:

  • Computer Science
  • Artificial Intelligence
  • Hardware Architecture

Background:

  • Linear systolic processor arrays are a proposed digital architecture for neural networks.
  • Efficient hardware implementation is crucial for deploying neural network models.

Purpose of the Study:

  • Analyze training algorithms on a linear systolic ring architecture.
  • Identify low-level instruction requirements for hardware implementation.
  • Assess hardware structures for processing elements (PEs) and array controller designs.

Main Methods:

  • Implemented and analyzed various training algorithms on a linear systolic ring.
  • Derived quantitative data on instruction requirements and hardware performance.
  • Evaluated different PE and array controller designs.

Main Results:

  • Identified specific low-level instruction needs for training algorithms.
  • Determined optimal hardware structures for PEs and controllers.
  • Provided data for cost-effective hardware construct selection.

Conclusions:

  • The analysis provides a foundation for designing efficient systolic array hardware for neural networks.
  • Cost-effective PE and controller designs were identified based on quantitative data.
  • This research contributes to the practical implementation of neural network hardware.