Comparison of floating gate neural network memory cells in standard VLSI CMOS technology

Area of Science:

• Solid State Physics
• Microelectronics Engineering
• Artificial Intelligence Hardware

Background:

• Floating gate MOSFETs are crucial for analog memory applications, particularly in neural networks.
• Standard CMOS processes offer a viable platform for fabricating these memory elements without specialized techniques.
• Evaluating different structures is essential for optimizing performance in analog neural network applications.

Purpose of the Study:

• To fabricate and compare various floating gate MOSFET structures for analog memory in neural networks.
• To identify the most suitable structure based on key performance criteria.
• To propose an optimized layout for analog neural network memory elements.

Main Methods:

• Fabrication of multiple floating gate MOSFET structures using a standard 2 µm double-polysilicon CMOS process.
• Characterization of physical and programming properties (charging/discharging symmetry, voltage magnitudes, area).
• Comparative analysis against literature data and evaluation based on geometric field enhancement effectiveness.

Main Results:

• Identified optimal designs that do not require special fabrication or 'field enhancement' techniques.
• Determined that using the poly1 to poly2 oxide for injection and poly1 to diffusion oxide for coupling capacitors is advantageous.
• Established that appropriate sizing of capacitor ratios is key to achieving a wide range of programming voltages.

Conclusions:

• The study successfully identified key design principles for effective analog neural network memory elements.
• Optimal structures leverage standard CMOS fabrication, specific oxide layers, and capacitor ratio engineering.
• The proposed layout offers a novel approach to analog neural network memory based on explored criteria.