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The TInMANN VLSI chip.

M Melton1, T Phan, D S Reeves

  • 1Dept. of Electr. and Comput. Eng., North Carolina State Univ., Raleigh, NC.

IEEE Transactions on Neural Networks
|January 1, 1992
PubMed
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A novel digital architecture, TInMANN, functions as a Kohonen self-organizing feature map. This design enables fast, dense, and reliable neural chip processing for complex data.

Area of Science:

  • Computer Science
  • Artificial Intelligence
  • VLSI Design

Background:

  • Kohonen self-organizing feature maps (SOFMs) are crucial for unsupervised learning and data visualization.
  • Implementing SOFMs in hardware offers significant speed and efficiency advantages over software-based approaches.
  • Existing hardware implementations often face limitations in scalability, cost, or performance.

Purpose of the Study:

  • To introduce TInMANN, a massively parallel, all-digital, stochastic architecture for Kohonen self-organizing feature maps.
  • To present a VLSI design for a TInMANN neuron suitable for cost-effective fabrication.
  • To demonstrate the performance capabilities and ease of synthesis for building large-scale neural networks.

Main Methods:

  • Development of a TInMANN neuron architecture using a silicon compiler (OASIS).

Related Experiment Videos

  • Integration of level-sensitive scan logic for automatic testability.
  • VLSI design targeting a small, inexpensive MOSIS TinyChip frame.

    • Main Results:

    • The TInMANN neuron operates at 15 MHz, processing 195,000 3D training examples per second.
    • The neuron design was synthesized in three man-months, allowing for performance trade-off analysis.
    • Achieved 100% fault coverage due to automatic testability features.

    Conclusions:

    • TInMANN provides a fast, dense, and reliable neural chip solution for SOFMs.
    • The architecture is scalable and cost-effective, enabling arbitrary network sizes.
    • The design facilitates efficient processing of large, high-dimensional datasets.