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An analog implementation of discrete-time cellular neural networks
H Harrer1, J A Nossek, R Stelzl
1Tech. Univ. of Munich.
IEEE Transactions on Neural Networks
|January 1, 1992
Summary
This study introduces a novel analog circuit for discrete-time cellular neural networks (DTCNNs), utilizing conductance multipliers and operational transconductance amplifiers for efficient computation. Fabricated and tested, the circuit demonstrates functional behavior for complex neural network applications.
Area of Science:
- Analog Circuit Design
- Neural Network Hardware
- VLSI Systems
Background:
- Discrete-time cellular neural networks (DTCNNs) are crucial for complex computational tasks.
- Efficient analog circuit implementations are needed to overcome the limitations of digital systems.
Purpose of the Study:
- To introduce a novel analog circuit structure for realizing DTCNNs.
- To demonstrate the feasibility of the proposed circuit through simulation and fabrication.
Main Methods:
- The circuit employs balanced clocked operations, conductance multipliers, and operational transconductance amplifiers.
- A layout was designed for a standard CMOS process, followed by HSPICE simulations.
- A 16-cell test chip was fabricated for experimental validation.
Main Results:
- HSPICE simulations confirmed the circuit's performance.
- Fabricated test chip measurements validated the transfer characteristics.
- Functional behavior was successfully demonstrated for a basic application.
Conclusions:
- The proposed analog circuit structure is a viable and efficient method for implementing DTCNNs.
- The design is adaptable to various neighborhood sizes and grid topologies.
- This work contributes to the advancement of hardware implementations for neural networks.
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