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Spatial versus temporal stability issues in image processing neuro chips.

T Matsumoto1, H Kobayashi, Y Togawa

  • 1Dept. of Electr. Eng., Waseda Univ., Tokyo.

IEEE Transactions on Neural Networks
|January 1, 1992
PubMed
Summary

This study clarifies stability issues in CMOS image processing neuro chips. It provides conditions for temporal and spatial stability, crucial for reliable neuro chip operation.

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Area of Science:

  • Neuro-engineering
  • VLSI design
  • Image processing hardware

Background:

  • CMOS-based neuro chips utilize regular arrays of simple cell circuits for image processing.
  • Implementation in CMOS processes introduces inherent temporal and spatial stability challenges due to parasitic capacitors and array structure.

Purpose of the Study:

  • To clarify the spatial stability issue in image processing neuro chips.
  • To derive explicit conditions for both temporal and spatial stability based on circuit parameters.
  • To analyze the relationship between temporal and spatial stability and estimate processing speed.

Main Methods:

  • Analysis of temporal dynamics induced by parasitic capacitors in MOS transistors.
  • Investigation of spatial dynamics arising from node voltage distribution in array structures.

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  • Derivation of necessary and sufficient conditions for chip stability.

    • Main Results:

    • Clarification of spatial stability issues in CMOS neuro chips.
    • Explicit if and only if conditions for temporal and spatial stability derived.
    • Demonstration that the set of parameters where spatial stability differs from temporal stability has measure zero.
    • Theoretical estimates for image processing speed provided.

    Conclusions:

    • Understanding and controlling temporal and spatial stability are critical for functional CMOS image processing neuro chips.
    • The derived conditions enable precise parameter tuning for robust chip design.
    • The findings contribute to the development of faster and more reliable neuro-inspired hardware.