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Modeling phase noise in frequency dividers.

¹GTE Gov. Syst., Mountain View, CA.

IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control

|January 1, 1990

Summary

This study presents a noise modeling theory for frequency dividers, validated by measurements on emitter-coupled logic (ECL) dividers. Key noise sources identified include additive output and sampled input noise, impacting phase power spectral density.

Area of Science:

Electrical Engineering
Signal Processing
Physics

Background:

Noise is a critical factor affecting the performance of electronic circuits.
Frequency dividers are essential components in various electronic systems, including communication and computing.

Purpose of the Study:

To develop and validate a theoretical model for noise in frequency dividers.
To identify and quantify the primary noise sources in emitter-coupled logic (ECL) frequency dividers.

Main Methods:

Development of a theoretical framework for noise modeling in frequency dividers.
Experimental measurements on ECL frequency dividers to collect noise data.
Analysis of noise contributions from additive output noise, sampled additive input noise, and sampled output noise.

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Main Results:

The primary noise contributions in ECL dividers were identified as additive output noise and sampled additive input noise.
The output phase power spectral density was found to be dependent on the square of the input frequency and inversely proportional to the output frequency.
Sampled output noise was identified as the third most significant noise contributor.

Conclusions:

The presented theory provides a robust framework for understanding and modeling noise in frequency dividers.
The findings offer valuable insights for designing and optimizing frequency dividers with reduced noise susceptibility.
The study contributes to the body of knowledge on noise mechanisms in high-speed digital circuits.