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Cache write generate for parallel image processing on shared memory architectures.

C M Wittenbrink1, A K Somani, C H Chen

  • 1Dept. of Electr. Eng., Washington Univ., Seattle, WA.

IEEE Transactions on Image Processing : a Publication of the IEEE Signal Processing Society
|January 1, 1996
PubMed
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We invented a new cache write-generate mode. This mode significantly boosts performance for parallel image processing by enhancing memory bandwidth, CPU efficiency, cache hits, and reducing latency.

Area of Science:

  • Computer Architecture
  • Parallel Processing
  • Memory Systems

Background:

  • Cache memory is crucial for system performance.
  • Efficient data handling is vital for parallel image processing.
  • Existing cache write policies can be suboptimal for certain workloads.

Purpose of the Study:

  • To introduce and evaluate a novel cache write-generate mode.
  • To assess the performance improvements of the new cache mode.
  • To analyze the impact on key system metrics for parallel image processing.

Main Methods:

  • Register-level simulations were employed for detailed analysis.
  • The simulation environment was validated using the UW-Proteus system.
  • Extensive evaluation across diverse memory, cache, and processor configurations was performed.

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Main Results:

  • The cache write-generate mode demonstrated significant improvements in main memory bandwidth.
  • CPU efficiency was notably enhanced with the new cache mode.
  • Reductions in cache latency and increases in cache hits were observed.

Conclusions:

  • The proposed cache write-generate mode offers substantial benefits for parallel image processing applications.
  • This invention presents a viable strategy for optimizing cache performance in demanding computational tasks.
  • The findings highlight the potential for architectural innovations to improve system-level efficiency.