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Compact parallel optical modified-signed-digit arithmetic-logic array processor with electron-trapping device.

G Li1, F Qian, H Ruan

  • 1Shanghai Institute of Optics and Fine Mechanics, Academia Sinica, PO Box 800-211, Shanghai 201800, China. gqli@ece.ucsd.edu

Applied Optics
|March 8, 2008
PubMed
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A novel optical processor performs addition and subtraction using a single set of binary logic operations, regardless of digit sign. This compact, high-signal-to-noise system simplifies optical computing.

Area of Science:

  • Computer Science
  • Optical Computing
  • Digital Arithmetic

Background:

  • Modified-signed-digit (MSD) arithmetic offers advantages in parallel computation.
  • Optical implementations can provide high speed and parallelism for arithmetic operations.

Purpose of the Study:

  • To propose and demonstrate a compact, two-step modified-signed-digit arithmetic-logic array processor.
  • To enable both addition and subtraction using the same logic operations, irrespective of input digit signs.

Main Methods:

  • Developed a two-step modified-signed-digit arithmetic-logic array processor.
  • Utilized optical implementation with an electron-trapping device for experimental demonstration.
  • Encoded each digit using a single pixel, eliminating the need for polarization.

Related Experiment Videos

Main Results:

  • Achieved addition and subtraction using identical binary logic operations.
  • Demonstrated a compact processor with a high signal-to-noise ratio.
  • Eliminated optoelectronic and electro-optic conversions for intermediate results.

Conclusions:

  • The proposed optical processor is compact, general-purpose, and simple to align.
  • This approach facilitates the execution of any combinational logic in optical systems.
  • The system offers efficient and sign-independent arithmetic processing.