320 Gbps to 10 GHz sub-clock recovery using a PPLN-based opto-electronic phase-locked loop

Area of Science:

• Optoelectronics
• Photonics
• Telecommunications

Background:

• High-speed optical data transmission relies on precise clock recovery for signal integrity.
• Existing clock extraction methods face challenges with increasing data rates and single-wavelength operation.

Purpose of the Study:

• To demonstrate a novel method for extracting a 10 GHz clock signal from high-speed OTDM data streams.
• To utilize nonlinear optical effects for phase comparison in clock recovery.

Main Methods:

• Employed an opto-electronic phase-locked loop (OEPLL) architecture.
• Utilized three-wave mixing in periodically-poled lithium niobate (PPLN) as the phase comparator.
• Tested with single-wavelength 160 Gbps and 320 Gbps OTDM data streams.

Main Results:

• Successfully extracted a stable 10 GHz clock signal from both 160 Gbps and 320 Gbps OTDM signals.
• Demonstrated the effectiveness of the PPLN-based phase comparator in the OEPLL.

Conclusions:

• The proposed OEPLL with a PPLN phase comparator is a viable solution for high-speed clock recovery.
• This technique supports efficient data processing in future high-capacity optical networks.