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Updated: Jul 3, 2026

Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology
Published on: December 7, 2015
Compatibility assessment of CVD growth of carbon nanofibers on bulk CMOS devices
Farzan A Ghavanini1, Hélène Le Poche, Jonas Berg
1Department of Microtechnology and Nanoscience, BioNano Systems Laboratory, Chalmers University of Technology, Göteborg, Sweden. Farzan@chalmers.se
Abstract:
We compare the level of deterioration in the basic functionality of individual transistors on ASIC chips fabricated in standard 130 nm bulk CMOS technology when subjected to three disparate CVD techniques with relatively low processing temperature to grow carbon nanostructures. We report that the growth technique with the lowest temperature has the least impact on the transistor behavior.
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