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Related Experiment Video

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Systematic Hearing Performance Evaluation Process for Adolescents with Cochlear Implantation at Early Ages

Systematic Hearing Performance Evaluation Process for Adolescents with Cochlear Implantation at Early Ages

Published on: March 24, 2023

Autonomous gain verification algorithm for a dual mode digital hearing aid chip.

Sunyoung Kim¹, Long Yan, Minsu Kim

¹Korea Advanced Institute of Science and technology, 373-1, Daejeon, 305-701, Republic of Korea. sunyoung@eeinfo.kaist.ac.kr

Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual International Conference

|January 24, 2009

Summary

This study introduces a novel digital hearing aid chip with an autonomous gain verification algorithm. This innovation ensures accurate hearing aid gain, improving performance and user experience.

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Area of Science:

Electrical Engineering
Biomedical Engineering
Signal Processing

Background:

Hearing aid technology requires precise gain control for effective sound amplification.
Conventional hearing aid models often lack real-time verification of acoustic gain, leading to potential inaccuracies.
Internal sound paths and vent effects can significantly influence real-ear gain measurements.

Purpose of the Study:

To propose and implement a dual-mode digital hearing aid chip featuring a real-time autonomous gain verification algorithm.
To analyze four distinct gain models considering different internal sound paths.
To compare the proposed algorithm's real-ear aided gain and real-ear occluded gain with conventional methods, accounting for vent and leakage effects.

Main Methods:

Development and implementation of a dual-mode digital hearing aid chip.
Design of a real-time autonomous gain verification algorithm.
Analysis of four gain models for different internal sound paths.
Evaluation of the chip in hearing aid mode and gain verification mode.

Main Results:

The algorithm accurately verifies real-ear aided gain and real-ear occluded gain, considering vent and leakage effects.
Convergence times for the algorithm range from 0.05 s (1 kHz) to 1.6 s (7.5 kHz).
The implemented chip demonstrates low power consumption (<130 microW at 0.9 V) and a small core area (5.4 mm^2) using 0.18 microm CMOS technology.

Conclusions:

The proposed dual-mode hearing aid chip and autonomous gain verification algorithm offer a viable solution for accurate and real-time gain adjustment.
The algorithm effectively accounts for internal acoustic variations, enhancing the reliability of hearing aid performance.
The chip's low power and small form factor are suitable for practical hearing aid integration.