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Updated: Jun 25, 2026

Fabrication of Gate-tunable Graphene Devices for Scanning Tunneling Microscopy Studies with Coulomb Impurities
Published on: July 24, 2015
Computational study of tunneling transistor based on graphene nanoribbon
Pei Zhao1, Jyotsna Chauhan, Jing Guo
1Department of Electrical and Computer Engineering, University of Florida, Gainesville, Florida 32611-6130, USA.
Abstract:
Tunneling field-effect transistors (FETs) have been intensely explored recently due to its potential to address power concerns in nanoelectronics. The recently discovered graphene nanoribbon (GNR) is ideal for tunneling FETs due to its symmetric bandstructure, light effective mass, and monolayer-thin body. In this work, we examine the device physics of p-i-n GNR tunneling FETs using atomistic quantum transport simulations. The important role of the edge bond relaxation in the device characteristics is identified. However, the device has ambipolar I-V characteristics, which are not preferred for digital electronics applications. We suggest that using either an asymmetric source-drain doping or a properly designed gate underlap can effectively suppress the ambipolar I-V. A subthreshold slope of 14mV/dec and a significantly improved on-off ratio can be obtained by the p-i-n GNR tunneling FETs.
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