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Flow-assisted Dielectrophoresis: A Low Cost Method for the Fabrication of High Performance Solution-processable Nanowire Devices
Published on: December 7, 2017
2007 IEEE Device Research Conference: Tour de Force Multigate and Nanowire Metal Oxide Semiconductor Field-Effect
Pengpeng Zhang1, Theresa S Mayer, Thomas N Jackson
1dagger Departments of Chemistry and Physics, double dagger Department of Electrical Engineering, The Pennsylvania State University, University Park, Pennsylvania 16802-6300, USA. ppz@nano.psu.edu
Abstract:
Scaling of the conventional planar complementary metal oxide semiconductor (CMOS) faces many challenges. Top-down fabricated gate-all-around Si nanowire FinFETs, which are compatible with the CMOS processes, offer an opportunity to circumvent these limitations to boost the device scalability and performance. Beyond applications in CMOS technology, the thus fabricated Si nanowire arrays can be explored as biosensors, providing a possible route to multiplexed label-free electronic chips for molecular diagnostics.
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