Scalable approach for vertical device integration of epitaxial nanowires

In this letter, we demonstrate the simultaneous vertical integration of self-contacting and highly oriented nanowires (NWs) into airbridge structures, which have been developed into surround gated metal oxide semiconductor field effect transistors (MOSFETs). With the use of conventional photolithography, reactive ion etching (RIE), and low pressure chemical vapor deposition, a suspended vertical NW architecture is formed on a silicon on insulator (SOI) substrate where the nanodevice will later be fabricated on. The vapor-liquid-solid (VLS) grown Si-NWs are contacted to prepatterned airbridges by a self-aligned process, and there is no need for postgrowth NW assembly or alignment. Such vertical NW architecture can be easily integrated into existing ICs processes opening the path to a new generation of nonconventional nano devices. To demonstrate the potential of this method, surround gated vertical MOSFETs have been fabricated with a highly simplified integration scheme combining top-down and bottom-up approaches, but in the same way, one can think about the realization of integrated nano sensors on the industrial scale.