Charge conduction and breakdown mechanisms in self-assembled nanodielectrics

Area of Science:

• Materials Science
• Electrical Engineering
• Nanotechnology

Background:

• Advanced gate dielectrics are crucial for next-generation transistors, including organic thin-film transistors (OTFTs).
• Self-assembled monolayers (SAMs) and multilayers, such as organosilane-based self-assembled nanodielectrics (SANDs), are explored as alternative high-k gate dielectric materials.
• Minimizing gate leakage current is essential for improving transistor performance and lowering operating voltages.

Purpose of the Study:

• To investigate the current-voltage-temperature (I(V,T)) transport characteristics of SAND types II and III.
• To understand how the pi-conjugated layer's position and the alkylsilane tunneling barrier influence leakage current in metal-insulator-metal (MIM) devices.
• To provide insights for designing improved self-assembled gate dielectrics.

Main Methods:

• Fabrication of Si/native SiO(2)/SAND/Au metal-insulator-metal (MIM) devices using SAND types II and III.
• Measurement of current-voltage characteristics over a temperature range of -60 to +100 degrees C.
• Analysis of charge transport mechanisms, including hopping, Poole-Frenkel, and Schottky transport.

Main Results:

• The placement of the pi-conjugated layer and the presence of a saturated alkylsilane tunneling barrier significantly control leakage current.
• For type II SANDs (pi-conjugated layer), hopping transport dominates at all measured temperatures.
• Type III SANDs (sigma-saturated + pi-conjugated layers) exhibit hopping transport above 25°C and a transition to tunneling below 25°C, with the alkylsilane barrier reducing leakage and promoting bulk-dominated (Poole-Frenkel) transport.

Conclusions:

• The combination of sigma- and pi-layers in SANDs, along with a suitable tunneling barrier, is critical for achieving low leakage currents.
• Bulk-dominated transport mechanisms are favored in type III SANDs, offering a pathway for enhanced gate dielectric performance.
• These findings guide the rational design of next-generation self-assembled gate dielectrics for advanced electronic devices.