Single-PPLN-based simultaneous half-adder, half-subtracter, and OR logic gate: proposal and simulation.

Area of Science:

• Photonics and Optical Computing
• Nonlinear Optics
• Integrated Photonics

Background:

• All-optical logic gates are crucial for high-speed optical communication systems.
• Previous implementations often require complex setups or multiple components.
• Simultaneous execution of multiple logic functions in a single device is highly desirable.

Purpose of the Study:

• To propose and simulate a novel all-optical simultaneous half-adder, half-subtracter, and OR logic gate.
• To achieve high-speed operation at 40 Gbit/s.
• To utilize a single periodically poled lithium niobate (PPLN) waveguide for simplified integration.

Main Methods:

• Cascaded sum-frequency generation (SFG) and difference-frequency generation (DFG) processes within a single PPLN waveguide.
• Utilizing SFG for the Borrow output and DFG for the Carry output.
• Combining SFG+DFG outputs to achieve Sum/Difference and OR logic functions.

Main Results:

• Successful simulation of simultaneous half-adder, half-subtracter, and OR logic gate operations.
• Demonstrated high-speed performance at 40 Gbit/s.
• Analysis of key performance metrics including eye diagrams, pulse width, quality-factor (Q-factor), and extinction ratio (ER), indicating impressive operational performance and tunability.

Conclusions:

• The proposed all-optical logic gate design based on cascaded SFG+DFG in a single PPLN waveguide is effective for simultaneous multi-functionality.
• The demonstrated performance metrics suggest the viability of this approach for future high-speed optical processing.
• This work offers a promising pathway towards compact and efficient integrated optical logic circuits.