Metal-Semiconductor Junctions
Biasing of Metal-Semiconductor Junctions
Field Effect Transistor
Characteristics of MOSFET
Biasing of FET
MOSFET: Enhancement Mode
You might also read
Articles linked to this work by shared authors, journal, and citation graph.
Updated: Jun 18, 2026

Fabrication of Gate-tunable Graphene Devices for Scanning Tunneling Microscopy Studies with Coulomb Impurities
Published on: July 24, 2015
1School of Electrical and Computer Engineering and Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana 47907, USA. sui@purdue.edu
This study investigates multilayer graphene field-effect transistors, revealing unique thickness-dependent performance. A resistor network model explains charge distribution and noise reduction in these advanced electronic devices.
Area of Science:
Background:
Purpose of the Study:
Main Methods:
Main Results:
Conclusions: