On VLSI Design of Rank-Order Filtering using DCRAM Architecture.

Area of Science:

• VLSI design
• Digital signal processing
• Computer architecture

Background:

• Rank-order filtering (ROF) is crucial for real-time speech and image processing.
• Existing ROF designs often face challenges in achieving high speed and low cost.
• Efficient hardware implementations are needed to meet the demands of modern applications.

Purpose of the Study:

• To propose a novel VLSI architecture for rank-order filtering (ROF).
• To introduce a specialized memory structure, the dual-cell random-access memory (DCRAM), for ROF operations.
• To achieve high-speed, low-cost, and flexible ROF implementation for real-time applications.

Main Methods:

• Utilized a generic bit-sliced ROF algorithm.
• Developed a memory-oriented architecture incorporating the dual-cell random-access memory (DCRAM).
• Implemented DCRAM operations including bit-sliced read, partial write, and pipelined processing, driven by maskable registers.

Main Results:

• The proposed ROF processor demonstrates high flexibility, low cost, and high speed.
• Physical implementation using TSMC 0.18 microm 1P6M technology resulted in a core size of 356.1 × 427.7 microm(2).
• The VLSI implementation achieved an operating frequency of 256 MHz at a 1.8V supply.

Conclusions:

• The proposed memory-oriented VLSI design effectively implements rank-order filtering.
• The dual-cell random-access memory (DCRAM) enables efficient threshold decomposition and polarization.
• The design offers a promising solution for high-performance, cost-effective real-time signal processing applications.