Related Experiment Video
Updated: Jun 18, 2026
10:58
A Procedure for Implanting Organized Arrays of Microwires for Single-unit Recordings in Awake, Behaving Animals
Published on: February 14, 2014
A low-power area-efficient 8 bit SAR ADC using dual capacitor arrays for neural microsystems
1Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI 48109 USA. schang@umich.edu
Summary
This study presents an 8-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for brain interfaces, achieving an 8x reduction in area and power. This efficient design offers significant advantages for miniaturized neural microsystems.
Area of Science:
- Electrical Engineering
- Biomedical Engineering
- Microsystems Design
Background:
- Brain signal interface microsystems require highly efficient Analog-to-Digital Converters (ADCs) for data acquisition.
- Conventional ADCs often face limitations in terms of chip area and power consumption, hindering miniaturization.
- Optimizing ADC performance is crucial for developing advanced neural interfaces.
Purpose of the Study:
- To develop an area-efficient 8-bit Successive Approximation Register (SAR) ADC.
- To significantly reduce power consumption for brain signal interface applications.
- To demonstrate an architecture capable of exponentially increasing area and power reduction with higher resolution.
Main Methods:
- Implementation of an 8-bit SAR ADC utilizing dual capacitor array banks.
- Minimization of chip area and power consumption through architectural innovation.
- Performance characterization including Signal-to-Noise and Distortion Ratio (SNDR), Spurious-Free Dynamic Range (SFDR), Total Harmonic Distortion (THD), and Effective Number of Bits (ENOB).
Main Results:
- Achieved an ultra-low power consumption of 680nW.
- Realized a compact chip area of 0.035 mm².
- Demonstrated an 8x reduction in area and power compared to conventional methods.
- Measured performance metrics: SNDR (42.82 dB), SFDR (57.90 dB), THD (-53.58 dB), and ENOB (6.65 bits).
Conclusions:
- The proposed dual capacitor array bank SAR ADC offers significant area and power efficiency for brain signal interface microsystems.
- The architecture shows potential for even greater efficiency gains at higher resolutions, with a factor of 16 reduction projected for 10-bit resolution.
- This advancement facilitates the development of smaller, more power-efficient neural interface devices.
