Adaptive resolution ADC array for neural implant.

Area of Science:

• Biomedical Engineering
• Neurotechnology
• Integrated Circuit Design

Background:

• Implantable prosthetic processors require efficient digitization of neural signals.
• Existing analog-to-digital converter (ADC) designs often face power consumption challenges in high-channel-count systems.

Purpose of the Study:

• To develop and characterize a novel ADC array with variable resolution for implantable neural signal processing.
• To reduce power consumption in neural recording systems through adaptive resolution techniques.

Main Methods:

• Implementation of a 96-cell ADC array using 0.13 microm CMOS technology.
• Design of a Successive Approximation Register (SAR) ADC base cell with adjustable resolution (3-8 bits).
• Dynamic adjustment of individual ADC cell resolution based on neural data content.

Main Results:

• Achieved variable resolution from 3 to 8 bits with power consumption ranging from 0.23 microW to 0.90 microW.
• Demonstrated an effective number of bits (ENOB) of 7.8 at the 8-bit setting.
• Reported a power consumption reduction by a factor of 2.3 through resolution adaptation, maintaining 7.8-bit effective resolution.

Conclusions:

• The developed variable resolution ADC array offers a power-efficient solution for neural signal digitization in implantable devices.
• Adaptive resolution is a viable strategy to significantly reduce power consumption in high-density neural recording systems.
• This technology supports the development of next-generation, long-duration implantable prosthetic processors.