A low power biomedical signal processor ASIC based on hardware software codesign.

Area of Science:

• Biomedical Engineering
• Digital Signal Processing
• Computer Engineering

Background:

• Biomedical devices require efficient digital signal processing for complex computations.
• Traditional software-based solutions often lead to high power consumption, limiting device portability and battery life.
• Hardware and software codesign offers a promising approach to optimize performance and power efficiency.

Purpose of the Study:

• To develop a low-power Application-Specific Integrated Circuit (ASIC) for biomedical digital signal processing.
• To leverage hardware and software codesign for enhanced system performance and design flexibility.
• To optimize the ASIC for low-power Fast Fourier Transform (FFT) calculations.

Main Methods:

• Employed a hardware and software codesign methodology.
• Integrated a low-power 32-bit RISC CPU (ARM7TDMI) and an AHB-compatible bus.
• Developed a scalable digital co-processor optimized for low-power FFT computations (8, 16, and 32-point).
• Simulated the design using ARM DSM and emulated on an ARM Versatile platform before silicon fabrication.

Main Results:

• Fabricated a multi-million-gate ASIC using SMIC 0.18 microm mixed-signal CMOS technology.
• Achieved a die area of 5,000 microm x 2,350 microm.
• Demonstrated low power consumption of approximately 3.6 mW at 1.8 V and 1 MHz clock rate.
• FFT calculation power consumption was less than 1.5% of conventional embedded software solutions.

Conclusions:

• The developed low-power ASIC effectively addresses the need for efficient digital signal processing in biomedical applications.
• Hardware and software codesign proved successful in achieving high performance and significant power savings for FFT computations.
• The ASIC offers a scalable and power-efficient solution for future biomedical device development.