Nanowire transistors without junctions.

Area of Science:

• Semiconductor Physics
• Materials Science
• Nanotechnology

Background:

• Existing transistors rely on semiconductor junctions, requiring high doping concentration gradients.
• Fabricating junctions below 10 nm presents significant challenges due to diffusion laws and atomic distribution.
• These limitations hinder the advancement of modern semiconductor devices.

Purpose of the Study:

• To propose and demonstrate a novel transistor design eliminating the need for junctions and doping gradients.
• To explore the fabrication and functionality of junctionless transistors using silicon nanowires.
• To evaluate the performance characteristics of these new devices compared to classical transistors.

Main Methods:

• Fabrication of transistors using silicon nanowires.
• Characterization of device functionality and performance metrics.
• Analysis of subthreshold slope, leakage currents, and carrier mobility.

Main Results:

• Demonstrated full CMOS functionality in junctionless transistors.
• Achieved near-ideal subthreshold slope and extremely low leakage currents.
• Observed less degradation of mobility with gate voltage and temperature compared to classical transistors.

Conclusions:

• Junctionless transistors offer a viable alternative to traditional designs, overcoming critical fabrication hurdles.
• Silicon nanowire-based junctionless transistors exhibit superior electrical characteristics.
• This technology holds promise for future high-performance, low-power electronic devices.