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Updated: Jun 14, 2026
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Micropunching Lithography for Generating Micro- and Submicron-patterns on Polymer Substrates
Published on: July 2, 2012
Selective electroless metallization of patterned polymeric films for lithography applications.
Daniel Zabetakis1, Walter J Dressick
1U.S. Naval Research Laboratory, Center for Bio/Molecular Science & Engineering (Code 6910), 4555 Overlook Avenue, S.W. Washington, DC 20375, USA.
ACS Applied Materials & Interfaces
|April 2, 2010
Summary
Researchers developed cost-effective methods for fabricating nanoscale electrical interconnects for shrinking computer chips. These processes create high-fidelity 50-nm metal features, addressing key manufacturing challenges in complementary metal oxide semiconductor (CMOS) technology.
Area of Science:
- Materials Science
- Electrical Engineering
- Nanotechnology
Background:
- Shrinking complementary metal oxide semiconductor (CMOS) devices necessitate advanced electrical interconnects for power and communication.
- Existing fabrication methods face significant material and processing compatibility challenges at submicron and nanoscale dimensions.
Purpose of the Study:
- To develop cost-effective, manufacturable processes for creating submicron and nanoscale metal features for electrical interconnects.
- To address material and processing constraints in CMOS device production.
- To enable fabrication of plasma-etch-resistant masks and metal diffusion barriers.
Main Methods:
- Utilized top-surface imaging and hybrid photoresist/self-assembled monolayer patterning.
- Employed selective electroless metal deposition.
- Focused on methods compatible with a manufacturing environment.
Main Results:
- Successfully fabricated metal features with approximately 50-nm width.
- Achieved high fidelity and sufficient edge acuity control to meet current industry design rules.
- Demonstrated potential for fabricating sub-10-nm metal features.
Conclusions:
- The developed processes offer a viable solution for fabricating critical nanoscale components for advanced microelectronics.
- These methods satisfy material and process constraints for CMOS device production.
- Further research can extend these techniques to even smaller feature sizes.
